Dennard Scaling: From Free Speed to the Power Wall

Halve transistor dimensions and voltage, and the ideal payoff is four times as many devices at twice the frequency, with unchanged chip dynamic power. Try dimension ratio 0.50 below.

That payoff is the promise of Dennard scaling. Chip area and switching activity stay fixed. It works only when voltage falls with dimensions; practical voltage limits break the power balance. Moore's law tracks component count, while Dennard scaling relates dimensions, voltage, speed and power. To see why the two can diverge, start with the geometry.

Smaller dimensions, smaller voltage

Let $s$ be the new linear dimension divided by the original dimension. A shrink to $s=0.7$ makes each dimension 70% of its former size. A shrink to $s=0.5$ halves it. These are physical dimension ratios in a teaching model, not ratios of modern process-node marketing names.

Constant-field scaling reduces horizontal dimensions, vertical dimensions and applied voltages by the same factor. Since electric field is roughly voltage divided by distance, its scale remains unchanged:

This is a coordinated device redesign, including doping and threshold behavior, rather than simply drawing a shorter gate. The original Dennard et al. paper develops these device relationships and summarizes circuit scaling in Table I, printed page 265. Its shrink factor is written inversely to $s$ here.

Area scales in two dimensions, so a device occupies $s^2$ of its old footprint. Keeping chip area fixed gives a device-density ratio of $1/s^2$. At $s=0.7$, that is approximately $2.04$: roughly twice as many devices in the same area.

Capacitance also changes. For the simple gate-capacitance approximation $C \propto A/t$, the gate area scales by $s^2$ and dielectric thickness by $s$. Their ratio leaves $C'/C=s$. A smaller device therefore needs less charge moved to switch its state.

Why the ideal device switches faster

A rough switching delay is charge divided by drive current: $\tau \sim CV/I$. In ideal constant-field scaling, capacitance, voltage and current each scale by $s$. Consequently:

The smaller transistor supplies less current, yet the charge it must move falls even faster. That is how lower current and faster switching can coexist. Treat the frequency ratio as an ideal device/circuit reference: a processor's achievable clock also depends on its critical paths, wiring and circuit design.

Faster switching alone would raise power. Lower voltage supplies the other half of the bargain.

The dynamic-power balance

The usual CMOS switching-power model is:

Here $\alpha$ describes switching activity, $C$ is switched capacitance, $V$ is supply voltage and $f$ is frequency. Keep activity fixed when comparing devices. The energy drawn per switching event is proportional to $CV^2$, so its ideal ratio is $s^3$. Switching more often, at frequency ratio $1/s$, gives per-device dynamic power $s^2$.

Now move from one device to a fixed-area chip. Multiply the device-density ratio $1/s^2$ by the dynamic-power ratio per device $s^2$:

Density and per-device power exactly cancel in this ideal model. Because chip area is unchanged, constant chip power also means constant power density. This calculation assumes the same mix of active devices and the same activity factor; filling extra area with different circuits would be a different comparison.

For a worked example, halve dimensions and voltage. Four devices now fit where one did before, and each can switch twice as fast in the ideal reference. Capacitance is halved, switching energy falls to one eighth, and power per device falls to one quarter. Four times the devices at one quarter the power each gives the original chip dynamic power.

This is the sense in which scaling offered “free speed”: higher ideal frequency and more devices without more dynamic power density. Fabrication was never free, and neither the derivation nor the figure promises that every program becomes faster by $1/s$.

Why voltage cannot keep following geometry

The ideal cancellation relies on $V'/V=s$. Lower supply voltage reduces the available drive above threshold, tending to slow switching unless threshold voltage also falls. Lower threshold, however, increases current through nominally off transistors. At a given temperature, conventional MOSFET subthreshold behavior does not shrink in proportion to geometry; the original paper already identifies that limitation on printed page 259.

Supply reduction also leaves less room to distinguish logic levels reliably. Noise margins, process variation and threshold variation constrain how low a practical circuit can go. These limits depend on the device, temperature and design requirements. There is no single universal voltage at which scaling suddenly stops.

In their 2007 scaling review, Dennard, Cai and Kumar discuss a leakage-constrained regime, constant-supply-voltage scaling and threshold variability. This is a constraint on continuing the ideal bargain, not a claim that voltage or energy efficiency can never improve again.

Leakage is separate from the switching-power equation. It consumes power even when a device does not switch, approximately $P_{\mathrm{leak}}=VI_{\mathrm{leak}}$. The following calculation excludes leakage so that the effect of constrained voltage remains visible on its own.

When the cancellation breaks

Separate the voltage ratio $v=V'/V$ from the dimension ratio $s$, and call the requested frequency ratio $g=f'/f$. Keep the capacitance approximation $C'/C=s$ and the fixed-area density $1/s^2$. Then:

The comparison below chooses the same ideal frequency target $g=1/s$ for both voltage cases. That target is a request, not a prediction that the voltage-constrained device can achieve it. Only its switching-power consequence is calculated.

The second case uses an authored illustrative floor $v=\max(s,0.7)$. The number 0.7 is a normalized teaching parameter, not 0.7 volts, a historical boundary or a model of transistor threshold. With $s=0.5$, the ideal case gives power ratio 1; holding voltage at 0.7 gives $0.7^2\times2/0.5=1.96$.

Toggle the voltage model at the initial 0.50 shrink, then raise the dimension ratio to 0.70 where the branches meet. The vertical budget mark is original chip dynamic power, normalized to 1, rather than a measured TDP or total-power limit.

The additional power demand has to be resolved somewhere. In this illustration, keeping $s=0.5$ and $v=0.7$ while limiting chip dynamic power to 1 would require $g=s/v^2\approx1.02$, far below the requested 2. That is a power-budget calculation, not a feasible operating-point prediction. A real design must also satisfy timing and include leakage, memory, wiring and other system costs.

The power wall changes the architecture question

When voltage and switching energy no longer fall enough to offset more active devices and higher frequency, cooling and power delivery constrain the combination a chip can sustain. This power wall turns “how many transistors fit?” into “which transistors should do useful work within the budget?”

Multicore designs spend some transistor capacity on multiple execution engines rather than relying only on a faster single core. That can increase throughput when a workload has independent work, but serial sections, synchronization and memory traffic limit the benefit. CPU pipelines still matter for each core, while distributed parallelism introduces additional communication costs.

GPUs make a different trade: many arithmetic operations share instruction control and exploit parallel work. They predate the breakdown of ideal scaling; the power wall strengthens the motivation to use throughput-oriented hardware where it suits the workload. A GPU cannot turn dependencies into parallel work, and memory access patterns can determine whether its arithmetic capacity is useful.

Specialization spends transistors on a narrower job to reduce energy per useful operation. Tensor cores, for example, organize computation around matrix operations. That advantage depends on supported operations, precision and data movement. Unused specialized units do not accelerate unrelated code.

Power constraints apply to multicore and accelerators too. The Dark Silicon research models the interaction between device power, chip organization and workload parallelism. Its projections are conditional research results, not measurements of every later processor. The architectural lesson is that more transistor capacity does not guarantee that all of it can run simultaneously at maximum frequency.

Dynamic voltage and frequency scaling, or DVFS, trades performance against energy and power by choosing an operating point. Lower frequency directly reduces switching power; lowering voltage can reduce it further through the squared term, provided timing still works. Power gating can reduce leakage in inactive regions. These techniques manage the budget rather than restore ideal constant-field scaling.

The causal chain is now complete: coordinated geometry and voltage scaling made smaller devices faster and cheaper to switch; practical voltage constraints weakened the power cancellation; architecture and software must choose parallelism, specialization and operating points that turn the available power into useful work. Additional transistors remain valuable, but their value depends on how they are used.

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